Microsoft Principal Design Technical Engineer 

Taiwan, Taoyuan City 

922339766

cutting edge

Technical Engineertechnical environment. You willbe responsible fordeveloping andthe RTL design flows and methodologies for ourcutting edgechip productions. Throughout the program you will be interacting with various teams, including architecture, front end design, verification,and physical design to ensure quality, performance and efficiency of RTL code and tool

Required qualifications:

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

• 8+ years of experience delivering successful Front End design using System Verilog or other HDL languages

• 8+ yearsexpertisein developing and deploying variousFront Endtools, flows and methodologies such as Lint, CDC,RDC, Synthesis

• 8+ years of experience in architecting and implementing end to end workflows that aid in RTL development that scale for IP,subsystemand full chip SOC

Other Requirements:

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate willbe requiredto provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable

Preferred qualifications:

• 10+ years technical engineering experience

o ORBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 14+ years technical engineering experience

o ORMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 11+ years technical engineering experience

o ORDoctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience.

• 10+ yearsexpertisein developing and deploying variousFront Endtools, flows and methodologies such as Lint, CDC,RDCand Synthesis

• 10+ years of experience in architecting and implementing end to end workflows that aid in RTL development that scale for IP,subsystemand full chip SOC

• track recordof architecting and implementing Front End RTL methodologies for multiple SOCs

• Thorough understanding of end-to-end SOC design cycles and dependencies between design, verification, physical design, DFT teams

• Proven ability to manage multiple projects simultaneously is a plus

• Experience working with global design, verification, physicaldesignand product teams

• Excellent communication skills

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: yMicrosoft will accept applications for the role until Oct 19th, 2025.

• Architect and implement workflows using industry-standard tools and best practices that aid in SOC assembly including RTL handoff between IPs/subsystems/SOC/DFT teams, hierarchy manipulation and feedthrough methodologies, constraint and waiver promotion, specification to design collateral flows etc.

• Provide guidance and training to the RTL design team on usage of the flows and methodologies

• toolsor flows

• Evaluate new tools, technologies and standards for RTL design and propose improvements and enhancements

• Document andmaintainthe RTL design flows and methodologies