Microsoft Principal Physical Design engineer 

Taiwan, Taoyuan City 

853560817

engineers to help achieve that mission.

and industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure.

PrincipalPhysical Design Engineer

• Bachelor's or master’s in electrical or computer engineering or related field with12+ years of experience

• Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level.

• Experience intapeoutsof complex ASICs in leading edge technology

• Experience in leading

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

a highly skilledand experiencedPhysical Designbe responsible forphysical design implementationand physical integration efforts to ensure the successful development ofsemiconductor products.

• PrincipalPhysical Design Engineer, you willbe responsible forPhysical Design tasks at block, subsystem, sub-chip, and/or full-chip level.  The tasks will includeFloorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM.  You may also be involved in Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection.

• at block/Sub System / Sub Chip / SOC level toset anddeliver quality results as perplanned milestone goals

• required