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Intel Circuit Design Engineer United States, Texas, Austin 894142919
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As a PROM Mixed-Signal Circuit Designer in DE your day-to-day responsibilities will include, but not always be limited to, utilizing the following skills:
- Develop, design and test PROM (Programmable Read Only Memory) circuits covering voltage level detectors, bandgap reference, charge pump, PROM arrays and analog to digital converters.
- Capture of design and measurement results to guide the next generation of process technology and circuit specifications based on requirements for critical analog and mixed-signal IPs.
- Physical validation of Hard IP to ensure it meets functional, timing, noise, and reliability requirements.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualification:Candidate must possess a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or related field.
Experience in the following:
- Analog/Mixed-signal Hard IP IC designs.
- Feature and specification definition of potential circuits such as Data Converter circuitsSwitched Capacitor CircuitsBandgap referencesop ampsbias circuitsRing OscillatorsCharge Pumps, etc.
- Exploration of novel, robust, competitive circuit solutions (considering power, area and performance) through feasibility studies including transient circuit simulation, Monte Carlo simulation, stability/Pole-Zero analysis, circuit aging and electrical overstress analysis.
- Circuit design convergence using industry standard design and validation tools.
- Device physics and process technology, especially as it applies to Analog/Mixed-signal designs.Preferred Qualifications:
Experience in the following:
- Experience in scripting languages (perl, tcl, etc.) to enhance design automation, verification, and delivery.
Experience in Post-Si debug from design perspective, including proposing tests and experiments, and reviewing results.
Effective schematic capture and behavioral modeling of circuits in Verilog, as well as logical equivalence verification between schematic and Verilog models.
Physical verification of circuit through layout-extracted static timing analysis (STA), electrical rules' check and noise analysis.
Reliability verification of layout: IR drop, electro-migration and self-heat analysis.
Layout strategies, and techniques (including analog techniques) to meet variance, timing, noise, and reliability requirements.
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