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Apple SerDes Circuit Design Engineer United States, Texas, Austin 384421712
28.03.2024
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Key Qualifications
- The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links.
- Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters
- In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
- Experience with Tx/Rx equalization techniques and circuits like de-emphasis, CTLE, DFE
- Experience with high speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.)
- Familiarity with CDR architectures and implementations
- Design experience in advanced CMOS technologies, design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization
- Experience in lab testing of high-speed serial links
- Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, SATA, etc.)
- EXPERIENCE IN THE FOLLOWING AREAS IS DESIRABLE:
- Static timing analysis tools (e.g., Nanotime, Primetime, etc.)
- Modeling of digitally assisted analog adaptive loops (using C, Matlab or Python, etc.)
- Able to build VerilogA/AMS behavioral models
- Able to analyze and lead characterization data from lab and volume testing
- Knowledge of ESD requirements
Description
We have ownership AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, clock generation and distribution, etc.)You will be working with multi-functional teams to define requirements/specs (e.g., modeling, package, board, DFT, ESD, etc.), crafting block-level specifications based on link-budget, behavioral modeling, and transistor-level feasibility. You will also drive mask design to implement layout view of designs. We also are working on Generation/QA of various IP Kit views/files for release to IP consumers, defining production/bench-level testplans, and conducting design reviews of blocks with peers/management to show design meets spec targets and requirements.
Education & Experience
BSEE with 10+ years of proven experience.
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