Master's degree or foreign equivalent in Electrical Engineering or related field and one year of experience in the job offered or related occupation
Education and/or experience with the following skills is required:
Experience with design rule checking (DRC) and implementation methodologies at both partition and top design levels.
Experience with layout versus schematic (LVS) verification
Leveraging Antenna (ANT) analysis to identify and mitigate potential reliability issues in integrated circuits
Guide partition floorplanning by incorporating recommended foundry requirements and group place and route (PNR) specifications.
Use Python, TCL, or Perl to debug and handle documentation.
Experience with the top and partition place and route (PNR) design process.
Experience with industry standard PNR tools such as Cadence, Synopsys, or Mentor Graphics.
Digital design fundamentals including understanding of digital logic design principles.
Knowledge of digital circuits and their functionality.
Working knowledge of related design principals in static timing analysis (STA), electrical analysis (EA), formal equivalence (LEQ), and low power design.