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Intel Physical Design Engineer United States, Texas 300547262
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As a Physical Design Engineer your responsibilities will include but are not limited to:
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimizes design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Behavioral traits that we are looking for:
Problem solving and analytical skills
Excellent in written and verbal communication
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.Education Requirement:
Bachelor's degree in Electrical Engineering or related field with 3+ years of work experience OR
Master's degree in Electrical Engineering or related field with 2+ years of work experience
Minimum Required Qualification:
2+ years of experience in the following:
Experience in Block/Top Floorplanning , Synthesis and PnR (preferably in complex Mixed-Signal blocks involving multiple analog blocks)
Experience in debug of LVS, DRC and other layout verification flows
Experience in one or more of the follow industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.)
Experience in one or more of the following scripting languages (eg. TCL, Perl, Python etc.)
Preferred Qualifications:
6+ years of experience in Physical Design
Synthesis and PNR flows on Multi-Voltage/Low Power designs with greater than 1M instances
Understanding of Logical Equivalence debug, Low power rule verification, Clock distribution schemes, Timing constraint analysis and feedback to Front-End teams, Static Timing analysis at block/top level.
Experience in scripting using EDA tool API interface for Cadence or Synopsys
Position of Trust
Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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