Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field and 3 years of experience in the job offered or related occupation.
3 years of experience with the following:
Experience in digital design to address LEC failures.
Debugging multiple partition failures for low power intent.
Utilizing CAD infrastructure to improve overall logic equivalency flow and method.
Experience automating regression for partitions and debugging.
Understanding lower power intent format and impact in detail for various projects.
Experience in TCL programming to improve overall efficiency.
Solving full chip level LEQ/PWRV failure.
Utilizing existing signoff process and flow to tape out high-quality products.