Intel FPGA Soft IP Design Verification Lead Engineer 

United States, California, San Jose 

813750492

Key Responsibilities:

· Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks. The plan encompasses functional, system level and hardware verification and validation perspectives.

· Developing IP/subsystem/system level testbench, creating tests, and necessary coverage goals based on specification to verify the implementation. Writing directed and random test cases, debugging failures, filing and closing bugs.

· Reviewing verification and validation results against the coverage goals. Writing, analyzing and achieving coverage metrics.

· Work with cross-functional teams and prepare/support IP functional validation tests for IP bring-up on actual FPGA development kits maximizing FPGA hardware capability to bring substantial improvement to IP quality and usability for Altera FPGA IP product portfolios.

· Integration of Synopsys VIP and their usage to aid end to end testing Ethernet/MACSEC/IPSEC protocol testing.

· Developing verification and validation tools and flows, as needed.

· Apply advanced techniques to achieve verification and validation with the highest quality, productivity, and time-to-market.

· Excellent communication skills.

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

· BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study plus 8 years of industry experience.

· 8+ years of experience developing verification collateral in Verilog, System Verilog, and UVM.

· 7 years with Ethernet protocol verification is required.

· Fluency in UVM, must have 7 years prior work experience with complex coverage driven random constraint UVM environments.

· Should have expertise in network security protocols: Ethernet/MACSEC/IPSEC end to end testing. Prefer candidates to be well versed in PCIe and Memory security solutions.

· 7 years of experience creating test plan from High level Specification and developing test cases.

· 7 years of experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.

· 4+ years of leading complex projects and leadership experience working with cross functional teams.

Preferred Qualifications:

· Must have put together complex UVM environments from scratch.

· FPGA experience is a plus.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing BenefitsAnnual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience