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Apple Design Verification Engineer United States, California, San Diego 803343378
06.05.2025
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In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to perform the following tasks:
- BS degree in technical subject area and minimum 3 years of meaningful experience.
- Solid understanding of SystemVerilog test-bench language and UVM.
- Experience developing scalable and portable test-benches.
- Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
- Experience with serial protocols such as PCIe or USB Experience with IP verification methodology for IPs such as PHYs, PLLs etc.
- In lieu of UVM knowledge, C/C++ expert level knowledge.
- Working knowledge with one of the scripting languages: Python, Perl, TCL.
- Proven experience in formal verification methodology.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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