In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are encouraged to perform the following tasks:Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP design.