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Apple Design Verification Engineer United States, California, San Diego 911804628
06.05.2025
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Once you understand the details of design components and any associated system reference models, you will construct detailed test plans for various components of the design including use cases, through collaborative work with cross-functional teams. You will create coverage driven verification plans from specifications, review with multi-functional teams and refine to achieve coverage targets. You will architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models. Working closely with DV methodology architects, you will improve verification flow. In this role, you will also execute test plans from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions and report the verification progress against test plans and coverage metrics.
- Bachelor of Science degree and 3+ years of relevant industry experience.
- Strong knowledge of System Verilog and UVM.
- Good understanding of System C, C/C++, Python/perl.
- Experience in developing and establishing DV Methodologies.
- Ability to develop System Verilog Testbench with UVM methodology from scratch.
- Experience with constraint random testing, SVA, Coverage driven verification.
- Good test planning and problem-solving skills.
- Master of Science degree in Electrical Engineering/Computer Science.
- Experience in C/C++ modeling for design verification.
- Knowledge of 4G/5G cellular physical layer operation (3GPP).
- Experience with verification of embedded processor cores.
- Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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