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Create Verilog/System Verilog/UVM test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level
Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump
Run DV regressions & analyze coverage, triage & debug failures
Run gate level simulations
Work with the RTL designers on identifying design fixes as needed
Work with test engineers on delivering pre-Si DV testcases for silicon bring up
Participate in silicon bring up and post silicon ATE correlation
Knowledge of testability techniques and features (1149.1, 1149.6, 1687, 1500, Scan, Built-in-Self-Test, Loop-Back etc.) covering digital logic domain, embedded memories and PHY/IOs
JTAG/1500/1687 networks and languages BSDL, ICL and PDL
Experience in general design verification methodology, regressions, simulation and debug tools
Expertise in Verilog or System-Verilog
Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl)
Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues
Degree in Computer Engineering or Electrical Engineering or equivalent experience with evidence of exceptional abilities in DFT verification
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