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Define and review verification and validation testplans at both the unit and integration levels
Review and aid in developing the RTL design architecture and specification
Verify design functionality through writing reusable and scalable testbenches, scoreboards, assertions, and assembly tests
Execute coverage of various use cases, then feeding back to the testplans for closure
Integrate your IP or block into higher level testbenches, then perform cluster/integration level testing
Integrate and work with VIPs to stress-test our IPs for various protocols
Develop and maintain regressions, tools, infrastructure, and methodology
Functional bringup and debug on various platforms and tools
Degree in Electrical, Computer Science, Computer Engineering or equivalent experience
5+ years of work experience in designing, verifying, and validating complex hardware systems
Solid programming skills in UVM, Verilog, System Verilog and Python
Proficient in debugging CPU, GPU, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs
Knowledge of advanced computer architecture and micro-architecture concepts
Experience with writing directed and random test cases
Experience with power and performance modeling concepts
Experience with hardware-software interaction, and software application testing on the chip is preferred
Emulation/FPGA experience is preferred
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