Cisco Test Timing Engineer 

United States, California, San Jose 

770802553

Your Impact

You are a detail-oriented Test Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate effectively with cross-functional teams, communicate complex timing data clearly, and are always focused on driving designs to closure. Responsibilities will include:

• Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.
• Check timing for unconstrained endpoints, no clock, etc.
• Your role may include SDC validation, CDC delay check, and SDC flow development.
• STA runs, more specifically at scan modes along with advising the Physical Design team on best practices.
• Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

Minimum Qualifications

• Bachelor’s degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience.
• Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes).
• Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus.
• Programming skills in at least 2 or more of the following languages: Perl, TCL, Python, Makefile, or other relative scripting languages.

Preferred Qualifications

• Master’s Degree in electrical or computer engineering (or other equivalent field) with 6+ years of related work experience.
• Thorough understanding of noise, cross talk, OCV, Sigma effects and Liberty file formats including standard cells/memory/IO/IP modeling and its usage in the ASIC flow.
• Background in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
• Prior working experience with SDC debugging & STA tools: Synopsys GCA/TCM/Primetime, Cadence CCD/Tempus.
• Strong communication skills and team player.

Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.