Intel Lead Timing Engineer 

United States, California, San Jose 

645587459

Key Responsibilities:

• Perform timing analysis and optimization, generate and verify timing constraints, and fix timing violations at the chip/block level for SoCs.
• Conduct timing rollups, design for functionality, and develop performance and power-optimized clock networks.
• Develop and define methodologies to ensure the highest quality of timing models, enabling the physical design team to operate efficiently.
• Define the appropriate process, voltage, and temperature (PVT) conditions for timing analysis based on product plans such as operating conditions and binning.
• Collaborate closely with the clocking team and other backend full-chip designers for clocking balance, timing fixes, power delivery, and partitioning.
• Work with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validate high-performance, low-power clock network guidelines.

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Requirements:

• Bachelor's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience
• Master's degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 6+ years of industry work experience
• PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 4+ years of related work experience
• Experience in creating functional and test mode constraints for Static Timing Analysis.
• Ability to close timing for designs with multiple clock domains, resets, and power supplies.
• Experience with different styles of resets, clock gating, synchronizers, FIFOs, etc.
• Experience with industry-standard timing EDA tools.
• Experience running multi-mode, multi-corner analysis.
• Knowledge of different signal integrity requirements and methods to analyze and fix issues.
• Experience with timing and functional ECOs.
• Proven track record of closing major designs with the latest technology nodes.

Preferred Qualifications:

• Proficiency in scripting languages such as Python, Perl, or TCL.
• Experience in developing and optimizing timing models for complex digital designs.
• Expertise in creating and managing constraints for RTL synthesis.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing BenefitsAnnual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00
*Salary range dependent on a number of factors including location and experience