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What you'll be doing:
As a Clocks team member, you will be collaborating with other architects, ASIC designers and verification engineers to design high frequency clocks.
You should be able to engage with multiple teams and design the SOC clocks to satisfy all the architectural constraints.
Your understanding of System Verilog will be valuable to verify the clocks design.
Together with other team members, we deliver clock information to SOC verification team, timing and DFT teams. You will use Perl to improve the productivity of the above teams.
Collaborate with Software and product design team to debug SOC clock silicon bugs in our new products.
What we need to see:
BS in Electrical Engineering or equivalent experience (MS preferred)
7+ years of relevant work experience.
Ability to thrive in a dynamically changing environment.
Experience in RTL design (Verilog), verification and logic synthesis.
Strong coding skills in Perl or other industry-standard scripting languages.
Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
Implementing on-chip clocking networks is a bonus.
You will also be eligible for equity and .
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