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What you will be doing:
Be an integral part of the team defining and developing highly configurable internal EDA software
Define, develop, and automate flows and methodologies to efficiently build, deploy, and verify generated RTL
Verify the generated code in multiple environments (functional/UVM, power, area, RTL checks like lint and CDC)
Work with EDA vendor tools (Synopsys) as well as industry standard scripting languages (Perl, Make, Python)
Interface directly with unit-level, Physical Design, CAD, Package Design, Software, DFT and other teams
What we need to see:
MS in Electrical or Computer Engineering with 4+ years of VLSI design experience, or BS (or equivalent experience) with 6+ years of experience
Good understanding of SOC architecture (e.g., CDC, multiple-power domains, performance analysis, latency, and data flow)
RTL Design experience in Verilog and/or SystemVerilog
Excellent debugging and analytical skills
Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Expertise in developing and implementing automated solutions within the ASIC flow
Strong coding skills in Perl or other industry-standard scripting languages
You will also be eligible for equity and .
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