Palo Alto Senior ASIC Integration CAD Engineer 

United States, California 

682251246

Being the cybersecurity partner of choice, protecting our digital way of life.

Your Career

As an ASIC Integration and CAD Engineer, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for performance, reliability, and power efficiency. You will integrate third-party IPs and PANW designs at the subsystem and top levels. You will guide the design team on strategies for clocks, resets, and synchronization. You will collaborate closely with the ASIC vendor and the PANW ASIC design team in floorplanning, closing timing, validating constraints, and optimizing power consumption.

Your Impact

• Integrate PANW designs at the subsystem and top levels, ensuring robust solutions for clocks, resets, feedthroughs, and DFT
• Integrate RAMs, CAMs, custom IPs, and IO pads throughout the design hierarchy
• Collaborate with external ASIC vendors to define optimal floorplans, power grids, clocking strategies, and custom routing
• Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption, and validating constraints

Your Experience

• BS in EE, CE, or CS required or equivalent military experience - MSEE preferred
• Minimum 5 years experience in ASIC integration and front end design
• Demonstrated success in taking ASICs to mass production
• Expertise in synthesis and static timing analysis
• Required strengths
  • Integrating RTL modules, memories, custom IPs, and IOs at multiple hierarchical levels
  • Implementing integration RTL in SystemVerilog
  • Good understanding of global clocking and reset schemes
  • Defining and validating timing constraints and exceptions
  • Closing timing with static timing analysis and verifying clock domain crossing paths
• Preferred experience
  • Creating automated flows for top-level integration
  • Physical synthesis with Fusion Compiler
  • RTL quality checks: Lint, CDC, RDC, X-verification
  • Physical design for networking ASICs with wide data paths and memory-dominant floorplans
  • Advising designers on optimizing congestion and power dissipation
• Skilled in writing powerful, modular, and scalable programs in Python / Perl / Unix shell to automate integration and physical design
• Demonstrated ownership and independence in planning, managing multiple priorities, driving vendors, and reporting status
• Strong leadership, collaboration, and communication skills

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $120000 - $193500/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found .

All your information will be kept confidential according to EEO guidelines.