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What you'll be doing:
As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms which include scan dump, array dump, and JTAG methodology.
Develop and deploy DFD methodologies and tools for our next generation products
Help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
BSEE (or equivalent experience) with 5+, MSEE (or PhD) with 3+ years of proven experience in DFT, DFD or related domains
Excellent analytical skills in verification and validation of test sequences and logic on complex and multi-million gate designs using vendor or in-house tools
Experience in Silicon debug and bring-up on the ATE and system level testing with an understanding of pattern formats, failure processing, and test program development
Proven knowledge and expertise in scan architecture, BIST including memories and IOs
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Strong programming and scripting skills in Perl, Python or Tcl desired
Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges
You will also be eligible for equity and .
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