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What you'll be doing:
As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, IO BIST, memory BIST, scan and array dump and DFX security methodology.
In addition, you will help develop and deploy DFT methodologies for our next generation products
You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
What we need to see:
BSEE or equivalent experience with 5+ years of experience, MSEE +3+yrs exp. (or PhD) with proven experience in DFT or related domains
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Knowledge of DFT security and hardware system security is a plus.
Strong programming and scripting skills in Perl, Python or Tcl desired
Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges
You will also be eligible for equity and .
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