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What you’ll be doing:
DFX planning, implementation, verification and silicon bring up at IP or fullchip level for NVIDIA's semiconductor products
Take lead role of some DFX areas in a project
Improve DFX design, architecture and flow
What we need to see:
BSEE with 3+, MSEE with 1+ years of experience or PhD in DFT or related domains
Familiar with Verilog and ASIC design
Solid understanding and expertise in JTAG, Scan, memory BIST, ATPG, and IO testing, etc.
Excellent analytical skills in verification and validation of test patterns and logic on sophisticated VLSI designs
Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing and diagnostics
Strong programming and scripting skills in Perl, Python or Tcl desired
Outstanding written and oral communication skills in English with the curiosity to work on rare challenges
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