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What you’ll be doing:
As part of the Operations Engineering team, you will drive our latest architecture designs to market
Identify and implement test processes to improve manufacturing efficiency for our latest Tegra/GPU/Automotive architectures, built in leading-edge process technology
Analyze product yield limiters, drive failures on Automatic Test Equipment (ATE) (Wafer and package level)
Lead multi-functional efforts with design, foundry, quality, test and suppliers to root-cause problems and implement improvements
You will have the opportunity to influence future ASIC designs to improve test coverage and enable better product yield, test time, silicon bring-up and releases
What we need to see:
Master's degree in Electrical Engineering or equivalent experience
5+ years of relevant experience
Critical thinking, solution focused
Experience with ASIC mixed-signal design, characterization and qualification
Knowledgeable in DFT and device physics
Proficient in statistical modeling of data using JMP software or other statistical tools
Excellent interpersonal skills, cross-functionally and between companies
Ways to stand out from the crowd:
Background with Automotive QUAL and Outlier Techniques
Previous experience working on SOC's andscripting/programmingknowledge (Python, Perl, etc)
Strong background in DFT techniques and advanced CMOS processes and examples of statistical data driven problem solving.
Hands-on experience with Verigy 93K tester/JMP
Skilled at collaborating with global teams, and an enthusiasm and real passion for the industry
You will also be eligible for equity and .
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