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What you’ll be doing:
As part of the Operations Engineering team, you will drive NPI bring-up of our latest architecture designs to market.
Identify and implement test processes to improve manufacturing efficiency for our latest SOC/CPU/iGPU architectures, built in leading-edge process technology.
Analyze product yield limiters, drive failures on Automatic Test Equipment (ATE) at Wafer and Package level
Lead multi-functional efforts with design, foundry, quality, test, customers and suppliers to root-cause problems and implement improvements
Characterize different aspects of performance and power to take competitive products to market
You will have the opportunity to influence future ASIC designs to improve test coverage and enable better product yield, test time, silicon bring-up and releases
What we need to see:
Master's degree in Electrical Engineering or equivalent experience
3+ years of relevant experience
Critical thinking, solution focused, and statistical data driven problem solving
Experience with Scan/Mbist/IObist DFT test coverage, PVTF silicon characterization and AEC-Q100 qualification
Knowledge indigital/analog/mixed-signalcircuits, fabrication process, device physics and advanced packaging
Proficient in statistical modelling of data using JMP software or other statistical tools
Excellent interpersonal skills, cross-functionally and between companies
Ways to stand out from the crowd:
Background in Automotive QUAL and Outlier Techniques
Experience with working on SOCs
Background in DFT techniques and advanced CMOS process
Previousscripting/programmingknowledge (Python, Perl, etc)
Hands-on experience with 93K ATE tester and JMP software
You will also be eligible for equity and .
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