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What you will be doing:
Drive our latest architecture designs to market!
Identify and implement test processes to improve manufacturing efficiency for our latest GPU architectures, built in powerful process technology
Analyze and root cause product yield limiters at wafer sort and package level on Automatic Test Equipment (ATE)
Lead multi-functional efforts with DFx, Design, Timing, Test, Foundry to root-cause complicated technical problems
Find creative solutions to complex problems and be on front-line to lead showstopper bugs
Have opportunity to influence future ASIC designs to improve product quality, test coverage to drive yields up and reduce waste
Master's degree in Electrical Engineering or equivalent experience
5+ years of experience
Critical thinking, solution focused and strong sense of ownership
Exposure to digital design and circuit analysis
Experience with product characterization on Verigy 93K tester and specification settings.
Proficient in statistical modeling of data using JMP software or other statistical tools for data analysis
Experience withscripting/programmingknowledge (Python or Perl)
Excellent interpersonal skills and highly skilled at collaborating with global teams
Background with DRAM/HBM Testing and 2.5D assembly
Experience with silicon reliability and aging mechanisms
Knowledgeable in DFT and foundry device physics process
You will also be eligible for equity and .
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