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Intel Mixed Signal IP Verification Engineer United States, Texas 627860044
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The Server DDRIO IP group within the DCAI is looking for a Pre-Silicon Verification Engineer to deliver latest and best-in-class DDR PHY IP for SoCs across Intel for the latest server products.
In this role you will perform all aspects of the functional verification flow to ensure design will meet specification requirements.
Who You Are
Responsibilities include but are not limited to:
You will perform IP Verification related tasks such as creating test plans, defining TB architecture and creating test benches, validating design and micro-architectural implementation.
You will be automating validation tasks to drive efficiently.
You will be analyzing results and help to debug issues in pre-silicon environment at IP, subsystem and SOC level.
You will collaborate with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
Capable of multitasking in a dynamic environment with multiple teams from different geos.
Solid verbal and written communication skills.
Excellent debug and problem-solving skills.
The additional responsibilities include:
Qualifications:You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must possess a BS degree in Computer Engineering/Computer Science/Electrical Engineering with 4+ years of relevant industry experience in Design verification, System Verilog and OVM/UVM., MS degree in Computer Engineering/Computer Science/Electrical Engineering with 2 years of relevant industry experience in Design verification, System Verilog and OVM/UVM.
The candidate must be experienced in validation flow right from test plan creation to verification closure, waveform debug, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS.
Preferred Qualifications
Knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols.
Experience in scripting skills in Python/Perl.
Exposure to Formal Property Verification and Git/Perforce/CVS version control
Position of Trust
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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