In this role, core responsibilities include, but are not limited to the following: • Review specifications and collaborate with the Design Team to extract features, define and execute verification plan. • Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests in a UVM framework. • Build and reuse real numbered analog behavioral models of the Analog and Mixed Signal Circuits.• Build and reuse monitors, and checkers for RF, Mixed-Signal and Digital blocks. • Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage. • Write scripts for automation of flow. • Improve Mixed Signal verification methodology.