Cisco Signal Integrity Engineer 

United States, California, San Jose 

593039562

You will define and design cutting-edge circuit boards (PCBs) and system interconnects, pushing the boundaries of technology.

Your role will involve collaborating with a diverse team of system architects, ASIC engineers, CAD engineers, software engineers, and other SI experts to create the next generation of high-performance networking products.

You will evaluate design tradeoffs, optimize performance, and ensure compliance with internal specifications and standards.

Your work will include electromagnetic modeling, gigabit serial link design, power delivery network analysis, and physical measurements for design validation.

BSEE combined with 4+ years of related experience.

EM knowledge with EM simulation tools such as HFSS and CST.

Hands-on experience with high-speed PCB/package development and high-speed NRZ and PAM4 Serdes.

Experience in power integrity design and analysis, and familiarity with PI simulation tools such as PowerSI/DC.

Experience in a lab with measurement tools (VNA, TDR, Real-Time Scope, BERT).

A self-motivated innovator with a strong desire to push the boundaries of technology.

Excellent teamwork and communication skills make you a valuable collaborator. You think outside the box and are always looking for new ways to innovate.

Expertise in electromagnetic simulation tools like HFSS and CST, combined with hands-on experience in high-speed PCB/package development, makes you a technical leader in your field.

Deep understanding of high-speed NRZ and PAM4 Serdes, power integrity design, and lab measurement techniques. Your strong lab skills and measurement experience with tools like VNA, TDR, Real-Time Scope, and BERT set you apart.

MSEE combined with 4 or more years of related experience

Experience working directly with ASIC, package, and system design teams to evaluate design tradeoffs and optimize performance, risk, cost, and manufacturability.

Experience in electromagnetic modeling of complex 3-dimensional structures.

Experience in designing and analyzing gigabit serial links and ensuring compliance with internal specifications and standards.

Experience in generating and verifying package layout rules and performing pre- and post-route signal integrity analysis of ASIC and PCB package designs.

Experience in modeling and analyzing power delivery networks.

Experience in conducting physical measurements to collect data for design validation and simulation correlations.