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Intel DFT Design Engineer United States, Texas 566805238
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The Design-for-Test (DFT) Implementation Engineer is a challenging and cutting-edge position working as part of a team to implement Design-for-Test capabilities on state-of-the-art silicon designs. You will be working with both external tier-1 customers and internal product design teams during their ASIC design cycle as they develop System-on-a-Chip (SoC) solutions utilizing CMOS cell-based ASIC technologies, along with integrated high-performance SerDes functions, embedded microprocessors, and high speed memory interface IP.
Who You Are
Your job responsibilities will include but not limited too:
- You will be responsible for development of the SoC Test Implementation plan describing the strategies to address the DFT requirements for the design, planning of the hierarchical test architecture, insertion of DFT structures, generation, simulation, and validation of test patterns for both DFT logic verification and for HVM ATE testing of the design, supporting the Static Timing Analysis (STA) team for the timing closure for the DFT modes of the design, and for supporting the Test Engineering team during silicon bring-up and New Product Introduction (NPI).
- You will also work closely with internal Test Methodology team and IP development teams.
- Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN)
- Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST)
- Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE)
- Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT. Optimizes logic to qualify the design to meet power, performance, area, timing, testcoverage, DPM, andtesttime/vectormemoryreduction goals as well as design integrity for physical implementation
- Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications
- Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure highquality integration of the IP block
- Collaborates with postsilicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
- Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
The ideal candidate will exhibit the following :
- Good problem-solving skills and a self-starter.
- Independently drive solutions to complex problems
- Ability to comprehend content of technical specifications for SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN
- Effective communication and collaboration skills.
- Ability to work effectively in a cross-site team environment.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Bachelor's degree in Electrical engineering, Computer science , Electronics and Communications Engineering with 6+ years of industry experience
- OR Master's degree in Electrical Engineering, Computer science, Electronics and Communications Engineering with 4+ years of industry experience
Your experience should be in the following:
- SoC Design-For-Test (DFT) principles including SCAN for logic testing, BIST and repair for memory test, JTAG Boundary SCAN
- Test insertion, test pattern generation, simulation, and verification
- Industry-standard DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax
- DFT architecture development and planning for an SoC
Preferred Qualifications:
- Knowledge of manufacturing tester capabilities, Automatic Test Equipment (ATE), and test program experience
- Knowledge of DFT integration of IP (e.g. DDR, SerDes, PLL's) into an SoC
- Static Timing Analysis, Synopsys PrimeTime, constraints and timing path debug
- Scripting Languages, e.g., PERL, TCL/Tk, Python
Position of Trust
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
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