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Job Area:
Engineering Group, Engineering Group > ASICS Engineering
Responsibilities
Run block level synthesis of digital HDL designs.
Optimize synthesis flow for power, performance, and area.
Run signoff tools to check timing, power and area goals are met!
Develop timing and low power design constraints
Run placement, clock tree synthesis, routing flows
Participate in design reviews
Identify areas for flow and process improvements.
Support the creation of ECO scripts to incorporate late design changes or timing fixes.
Desirable Skills and Experience
Great attention to detail and strong communication skills
Knowledge of synchronous digital design
Proficient in scripting languages (e.g. Perl, Python, TCL) and Linux shell usage
Experience of RTL design (e.g. verilog or VHDL) or static timing analysis
Previous exposure to commercial EDA tools (e.g. Design/Fusion Compiler, Innovus, Primetime, PTPX)
Hands-on experience developing timing constraints or CPF/UPF power constraints
Knowledge of Design for Test (Scan test, mbist)
Knowledge of physical design (Floorplanning, PnR, CTS etc)
Minimum Qualifications
What's on Offer
Apart from working in an open, relaxed and collaborative space, you will enjoy:
Salary, stock and performance related bonus
Employee stock purchase scheme
Matching pension scheme
Life, Medical, Income and Travel Insurance
Relocation Assistance (If required)
Enhanced Maternity Leave
Enhanced Paternity Leave
Menopause Support
Education Assistance
Employee Assistance Programme
Voluntary Health Checks
Complimentary Period Products onsite
Global Wellbeing Days
Subsidised gym membership
Bicycle purchase scheme
Employee run clubs, including, running, football, chess, badminton + many more
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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