The point where experts and best companies meet
Apple ASIC Design Engineer - Pixel IP United States, California, Cupertino 543258853
06.05.2025
Share
- BS and a minimum of 10 years relevant industry experience
- Experience in IP/SoC front-end ASIC RTL digital logic design using Verilog and System Verilog.
- Extensive shown experience in ASIC implementation, especially logic synthesis, static timing analysis, logic equivalence checking, and working with physical design teams for floorplanning and timing closure.
- Deep experience with system design methodologies that contain multiple clock domains.
- Practiced in low-power design issues, tools, and methodologies including UPF power intent specification.
- Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
- Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with relevant scripting languages (Python, Perl, TCL).
- Tight-knit collaboration skills with excellent written and verbal communication skills.
- Extensive experience working multi-functionally with integration, design, and verification teams to specify, design, and debug digital systems.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
These jobs might be a good fit
