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Apple ASIC Design Engineer - Pixel IP 
United States, California, Cupertino 
340103949

30.06.2025
  • Bachelors Degree in EE/CE with +3 Years of Experience.
  • Prefer previous experience in media, video, pixel, or display designs.
  • Experience in SoC front-end ASIC RTL digital logic design with using Verilog or System Verilog.
  • Experience working cross-functionally with architecture, design, and verification teams to specify, design, and debug designs.
  • Good collaboration skills with strong written and verbal communication skills.
  • Familiarity with low-power design techniques such as clock- and power-gating is a plus.
  • Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
  • Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks.
  • Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with and AI/ML applications, relevant scripting languages (Python, Perl, TCL).
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.