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Google ASIC RTL Engineer Silicon Taiwan, New Taipei 538413809
Yesterday
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- Experience with a scripting language like Perl or Python.
- Experience with ASIC or FPGA design verification, synthesis, timing/power analysis and DFT.
- Knowledge of high performance and low power design techniques, assertion-based formal verification, FPGA and emulation platforms and SOC architecture.
- Knowledge of memory compression, fabric, coherence, cache, or DRAM.
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