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Google CPU RTL Engineer Silicon 
Taiwan, New Taipei 
140965880

17.06.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with microprocessor architecture.
  • Experience with logic synthesis techniques to optimize RTL code, performance, power, and design techniques.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
  • Experience with modern processor micro-architecture and related technologies and algorithms.
  • Knowledge of Programming languages such as C, C++, and Python.
  • Knowledge of general purpose operating systems such as Linux or Android.