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Microsoft Principal Verification Engineer 
Taiwan, Taoyuan City 
537478872

Today

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIEis responsible fordesign, development,state of the artcustom computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategicadvantage

is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery,and industry knowledge to envision and implement future technical solutions that will manage andthe Cloud infrastructure

Required Qualifications:

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • OR equivalent experience.
  • 7+ years of experience working on Computer Architecture and SoC design and verification principles, including using industry standard HDLs like System Verilog.
  • 7+ years of experience developing and using verification environments in industry standard languages like SVTB UVM or formal verification.

Requirements

to meet Microsoft, customer and/or government security screening requirementsfor this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will beto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

  • 2+ years of pre-silicon verification technical leadership, including leading a team, technical scoping, and project planning.
  • Substantial background in architecting and developing SV/UVM testbenches.
  • Experience developing test plans, managing regressions, and triaging failures.
  • Experience reviewing and reacting to architecture definitions and changes.
  • Experience analyzing and closing code and functional coverage.
  • Experience developing C/C++ test cases.
  • In depthknowledge of full chip and system level flows and protocols.
  • expertisein one or more of the following:
  • DFD, JTAG, and debug protocols
  • Memory Controller/PHY IPs, DDR protocols, and related firmware/BIOS/MRC
  • CPU cores, protocols, and related firmware
  • Coherent and non-coherent fabric IPs and protocols
  • PCIe Controller/PHY IPs, protocols and related firmware
  • Manageability IPs, protocols, and related firmware
  • Security IPs, firmware, SoC level features/flows, OS/software interactions.
  • Collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.

Certain roles may be eligible for benefits and other compensation. Findbenefits and pay information here:


Responsibilities
  • Lead an SoC verification team, owning verification of SOC and integration ofit’scomponents and/or SoC level flows
  • Become knowledgeable on the overall SoC architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software.
  • Drive verification strategy, test plans, requirements, environments, tools, and methodologies.
  • Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
  • Run tests, debug failures to root cause, and recommend fixes.
  • Apply your growth mindset to learn and adapt in a complex and dynamic environment.
  • Engage with partners to drive continuous improvement to both the design, to verification plans/collateral, and tomethodologyto prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
  • Mentor and coach team members
  • Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers.
  • Embody our culture and values.