Cisco ASIC Physical Design Engineer 

Armenia, Yerevan 

519200619

As a member of the ASIC Physical Design Team, your role encompasses the full chip physical implementation, spanning from RTL to GDSII.

• Engage in full chip physical implementation, covering the process from RTL to GDSII, and collaborate with Front-End teams to understand design architecture for effective implementation.
• Perform gate-level netlist synthesis (physical synthesis) and execute physical implementation tasks such as floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
• Optimize design for power, performance, and area, and conduct formal verification to ensure design integrity.
• Perform Static Timing Analysis (STA), complete physical verification, and achieve signoff closure.
• Analyze and resolve Electromigration (EM) and IR-drop (IR) issues to meet signoff requirements.

You'll be part of a team of senior engineers skilled in managing complex projects. The culture values expertise exchange, collaboration, and celebrating successes. Whether you're experienced or have great potential, expect growth through sophisticated assignments and learning from top-tier colleagues.

• A Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5+ years of experience in ASIC design and verification.
• Proficiency in deep submicron CMOS technologies.
• Comprehensive knowledge of the full design cycle from RTL to GDSII.
• Strong understanding of Static Timing Analysis, timing closure, and design constraints.
• Expertise in block-level synthesis, place and route, and timing closure, with knowledge of industry-standard PnR and signoff tools.
• Excellent verbal and written communication skills in English.

• Work with Front-End teams to understand the design architecture to ensure optimal physical implementation
• Experience with gate-level netlist synthesis (physical synthesis).
• Proficiency in physical implementation tasks such as floorplanning, placement, clock tree synthesis (CTS), and routing.
• Skills in optimizing design for power, performance, and area optimization of design.
• Knowledge or experience in formal verification.
• Experience in Static Timing analysis/signoff closure, physical verification/signoff closure, EMIR analysis/signoff closure.

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)