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Google ASIC Design Testability Engineer Silicon India, Karnataka, Bengaluru 508158823
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree or equivalent practical experience.
- 4 years of experience in DFT/DFD flows and methodologies.
- Experience developing DFT specifications and driving DFT architecture.
Preferred qualifications:
- Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD.
- Experience with STA constraints development and analysis for DFT modes and SDF simulations.
- Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging.
- Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues.
- Knowledge of various test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL).
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