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Google ASIC Design Testability Engineer Silicon India, Karnataka, Bengaluru 337282577
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Minimum qualifications:
Preferred qualifications:
- Bachelor's or Master's degree or equivalent practical experience.
- 5 years of experience with Design for Testability/Design for Debugging (DFT/DFD) flows and methodologies.
- Experience in developing DFT specifications and DFT architecture.
- Experience in fault modeling, test standards and industry DFT/DFD/Automatic Test Pattern Generation (ATPG) tools with Application-Specific Integrated Circuit (ASIC) DFT, synthesis, simulation and verification flow.
Preferred qualifications:
- Experience with DFT for a subsystem with multiple physical partitions.
- Experience with Internal JTAG (IJTAG) ICL, Procedural Description Language (PDL) terminology, ICL extraction, Instrument Connectivity Language (ICL) modeling with Siemens Tessent Tool.
- Experience with Spyglass-DFT, DFT Scan constraints and evaluating DFT Static Timing Analysis (STA) paths.
- Experience with coding language like Perl or Python.
- Knowledge of DFT techniques like SSN, HighBandwidth IJTAG.
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