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Google ASIC Design Testability Engineer Silicon India, Karnataka, Bengaluru 331657091
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
- 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing.
- Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
- Experience with DFT EDA tools (e.g., Tessent).
Preferred qualifications:
- Experience with DFT for subsystems with multiple physical partitions.
- Experience with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent tool.
- Experience with Spyglass-DFT, and DFT Scan constraints, and evaluating STA paths.
- Experience in developing automated workflows using Python and Tcl.
- Experience in collaborating with Design, PD, and STA teams.
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