Cisco Physical Design Engineer 

United States, California, San Jose 

479410996

Your ImpactAs a physical design engineer you will be spearheading the implementation of complex multi-hierarchy designs, ensuring robust physical design processes like logic synthesis and static timing analysis. By resolving design challenges and driving the execution of innovative solutions, you will impact the successful delivery of high-quality ASIC and SoC designs, including the creation of custom macros, contributing to our team's efficiency and success. Responsibilities include:

• Develop and own physical design implementation of multi-hierarchy designs including physical aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
• Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design.
• Design custom macros like PLL, GPIO design and RDL connections.

Minimum Qualifications:

• BS in Electrical Engineering or Computer Science, with 5+ year minimum of hands-on experience in ASIC implementation and Physical verification.
• Hands-on experience in physical synthesis, floor planning, P&R, and timing closure of high-performance designs with a focus on improving PPA (Performance, Power, Area).
• Experience and knowledge of hardware architecture and RTL/logic design for timing closure, specifically experience in critical timing path planning and crafting.
• Expertise and hands-on knowledge of industry standard EDA tools for Synthesis, P&R and Timing.
• Experience with deep sub-micron process nodes and hands-on expertise in modeling and optimizing high-performance designs within these nodes.

Preferred Qualifications:

• MS in Electrical Engineering or Computer Science, with 3+ year minimum of hands-on experience in ASIC implementation and Physical verification.
• Experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support.
• Basic TCL and python scripting.
• Experience on 7nm nodes and below.
• Prior experience working with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical design teams.

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).