Cisco Physical Design Engineer 

United States, California, San Jose 

411802213

Who You'll Work With

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities

What You'll Do

You will be part of ASIC physical design Team which is responsible for full Chip physical implementation from RTL to GDSII. As Physical Verification Engineer your main responsibilities will include:

• Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results
• Work with block and top level implementation teams to understand physical aspects and feedback on necessary updates
• Work closely with block and TOP level physical implementation, IP development teams and to resolve PV issues and address to proper owners
• Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification robustness
• Support block and TOP implementation teams to solve local PV issues

Minimum Qualifications:

• BS/MS in Electrical Engineering or Computer Science, with 7+ year minimum of hands-on experience in ASIC implementation and Physical verification
• Prior experience in deep submicron CMOS technologies
• Prior experience with physical verification (DRC, LVS, ERC, ANT), debug and solution
• Experience in one of the scripting languages (Python, Tcl, Skill)

Preferred Qualifications:

• 7+ years of experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support
• Experience on 7nm nodes and below
• Prior experience working with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical design teams
• Previous work experience working with Package and floorplan teams to define padring and bump-map design
• Background in industry-standard physical verification EDA tools