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Google ASIC RTL Design Engineer Machine Learning Accelerators United States, California, Sunnyvale 437060125
05.08.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- 2 years of experience in Digital design using SystemVerilog RTL.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering or Computer Science.
- 4 years of experience in digital/ASIC design using SystemVerilog or RTL.
- Experience in one or more successful ASIC products from concept to silicon.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience defining SoC IP interfaces and methodologies.
- Understanding in computer architecture/memory subsystem architecture.
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