Cisco ASIC Design Verification Engineer 

United States, California, San Jose 

427949556

Who You'll Work With

You will engage in dynamic collaboration with verification engineers, designers, and cross-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

What You'll Do

You will contribute to developing Cisco’s revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

• Architect block, cluster and top-level DV environment infrastructure.
• Develop DV infrastructure from scratch for block, cluster and top-level environments.
• Maintain and enhance existing DV environments.
• Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and directed stimulus.
• Ensure complete verification coverage through implementation and review of code and functional coverage.
• Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
• Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and optimal performance.
• Support testing of design in emulation.
• Oversee and manage the ASIC bring-up process.

Minimum Qualifications

• Bachelor’s Degree in EE, CE, or other related field.
• 7+ years of related ASIC design verification experience.
• Proficient in ASIC verification using UVM/System Verilog.
• Proficient in verifying complex blocks, clusters and top level for ASIC.
• Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Scripting experience with Perl and/or Python.

Preferred Qualifications

• Master’s Degree in EE or CE with 5+ years of related work experience.
• Experience with Forwarding logic/Parsers/P4.
• Experience with Veloce/Palladium/Zebu/HAPS.
• Formal verification (iev/vc formal) knowledge.
• Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).