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Cisco ASIC Design Verification Engineer United States, California, San Jose 716577087
18.11.2024
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Who You'll Work With:
You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross functional teams to verify the ASIC in simulation, in emulation and during ASIC bring up
What You'll Do:
- Maintaining existing DV environments and enhancing them
- Construct testbench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop testcases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage
Minimum Qualifications:
- Bachelor's or Master's degree and 8 years of relevant experience required; prior experience with System Verilog and UVM methodology
- Prior experience in verifying complex blocks, clusters and top level for SoC
- Prior experience building testbenches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Prior experience with functional coverage and constrained random DV environments.
- Scripting skills: Perl and/or Python scrip
Preferred Qualifications:
- Strong domain experience on one or more protocols in a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
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