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Cisco ASIC Design Verification United States, California, San Jose 101705325
17.12.2024
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Who You Are:
You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, and hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.
You’ll be part of the Cisco Common ASIC Group, focusing on developing and upgrading various test benches and contributing to different aspects of verification infrastructure.
Responsibilities Include:
- Create block level test benches including components like drivers/monitors/sequences
- Maintaining existing test benches for block level and/or cluster level
- Upgrading test benches to accommodate new features
- End-to-end verification of various design blocks
- Developing test plans, cover points
- Upgrading/updating configuration/reset sequences (APIs)
- Collaboration with designers/verification engineers to perform cross-block verification
- Writing tests, and debugging regressions
- Contributing to top level verification
- Be a part of emulation testing efforts
Education and Experience Required:
- Master’s degree in EE (Electrical & Electronics) or CE (Computer Engineering) with 2+ YoE in Design Verification
- Bachelor’s degree in EE or CE and 3+ YoE in Design Verification
Knowledge and Skills:
- Hands-on and deep understanding of System Verilog and UVM methodology
- Ability to write System Verilog constraints, construct testbench including scoreboard, agents, sequencers, and monitors
- Ability to debug issues independently
- Proficient in functional coverage and constrained random DV environments
- Good written and verbal communication skills
- Collaborative and team-focused, with the drive to learn and grow
- Basic scripting experience (Python, Perl, shell programming)
- Nice to have C, C++ programming and debugging skills
Required Skills:
Nice to have Skills:
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