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Apple Design Verification Engineer United Kingdom, England, London 41874349
01.06.2024
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Description
Use SystemVerilog, UVM and C++ with industry leading simulation tools and methodologies to verify complex GPU designs.Develop verification plans in coordination with design leads and architectsCreate and maintain verification test bench components and environmentsGenerate directed and directed random testsRun simulations and debug design and environment issuesBuild functional coverage points, analyze coverage, and improve test environment to target coverage holesBuild automated verification flows for block verificationWork with other block & core level engineers to ensure seamless verification flow
Key Qualifications
- Expertise with verification languages such as SystemVerilog, Specman or Vera and verification methodologies such as UVM/OVM is a plus.
- Experience of working in complex ASIC or SOC designs
- Expertise with HDL simulators & waveform viewers
- Experience defining coverage space, writing coverage model, analyzing results
- Experience working under strict schedule deadlines with the ability to handle multiple priorities
- Graphics architecture and programming (OpenGL/OpenCL) highly desired. Strong knowledge of computer architecture, general purpose microprocessor and memory sub-system micro-architecture in lieu of graphics experience.
- Experience with scripting languages like Python, Go, Perl or Ruby a plus
- Excellent communication skills and ability to collaborate
Education & Experience
BS/MS CE or EE or related fields
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