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Develop system-level power features to address existing and new productopportunities/requirementsfornext generation GPU, CPU and SOC to optimize system level performance and power and transcend product goals.
Analyze exciting workload profiles to identify potential opportunities.
Providing input on pitfalls and opportunities during feature proposal reviews.
Work closely and proactively with other engineering teams such as system architects, chip and board designers, software/firmware engineers, HW/SW QA teams and Applications engineering teams to develop system level power management strategy/technique to optimize HW/SW performance and power management, drive design, development, debug and release of next generations products.
The prototype features on existing silicon/platforms, lead technical return-on-investment investigations, and design feature bring-up plans for new silicon.
Drive new feature/spec debug from HW side and provide creative solution to deliver the feature into productization to achieve high product quality at aggressive schedule.
BS or MS degree in EE/CE or equivalent experience.
Minimum of 8+ years working experience in Energy/Power/Perf Optimization in GPU/SOC, and ASICs.
Experience with ASIC power-saving features, system-level power-saving features, and experience optimizing products deploying multiple ASICs with shared power constraints.
Deep understanding of firmware/driver structures and their interaction with HW.
Working knowledge of PVT dependencies and binning methodologies.
Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.
Excellent verbal communication, written and presentation skills.
Effective in a collaborative environment.
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