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What you will be doing:
Bring up system level low power features to address existing and new productopportunities/requirements.Lead technical return-on-investment investigations, create/maintain feature bring-up plans for new silicon and participate in bring-up execution.
Lead debug efforts from HW side to root cause feature sequences bugs, silicon bugs and complex system level issues caused by interactions between multiple HW and SW features.
Craft creative solutions and WARs through lab experimentation and effective use of debug tools, to achieve high product quality at extremely aggressive schedules.
Support manufacturing and customer facing teams to expertly address production needs and issues on the relevant features.
Work closely and proactively with other engineering teams such as system power architects, chip and board designers, software/firmware engineers, HW/SW QA teams and Applications engineering teams to drive low power design, development, debug and release of next generations products.
What we need to see:
BS/MS (or equivalent experience) with 12+ years of proven ability in the area of silicon characterization and productization with focus on lower power system features.
Exposure to Windows, Linux based Low Power states and Silicon Power behavior, power analysis, process technologies, transistor/device physics, silicon reliability and aging mechanisms.
Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting
Hands-on validation lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers).
Experience with ASIC power saving features and methods
Deep understanding of firmware/driver structures and their interaction with HW.
Excellent problem solving, teamwork, and interpersonal skills.
Background with automation scripting in languages such as Perl, Python, tcl.
You will also be eligible for equity and .
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