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Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Responsible for next-generation workflow automation for TECH IP engineers.
Design, develop, deploy, and improve highly scalable, long shelf-life workflows and automation platforms for compute and memory-heavy workloads.
Deconstruct user workflows into actionable tasks and plan a pathway to automation.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
Master’s degree in Engineering, Computer Science, or a related technical field.
With 5+ years of experience in software development, and with data structures/algorithms
With 5+ years of python coding experience
Excellent grasp of workflows and UNIX processes, concurrency and load-balancing
Experience seeking and solving problems in partitioning and optimizing existing interconnected systems
Understand LSF infrastructure is a plus
Exposure to Perl, Make and VLSI flows is a plus
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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