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What you'll be doing:
Work in advanced technologies and develop behavioral model and verification for custom mixed signal design cells that would be used on all the NVIDIA products.
Use proficiency of Verilog, SystemVerilog, Perl, or Python and understanding of DDR and other high-speed interconnects to verify, emulate/prototype, and perform lab bring up.
Collaborate with cross function teams with regards to library issues and cell integration to customer ASIC design environment.
Document, execute, and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
What we need to see:
Bachelors and/or Masters in EE/CE or relevant field (or equivalent experience)
Hands-on experience with scripting languages(Makefile/Perl/Python).
Fundamental digital design concepts and experience.
Ability to collaborate with many groups and communicate technical details effectively.
You will also be eligible for equity and .
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