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What you’ll be doing:
Work on a unit level testbench, working on directed and random tests and test infrastructure, and contributing to the future direction of the methodology for the testbench
Partner closely with RTL and architecture teams to help refine the microarchitecture plans to ensure that changes to the design are verifiable
Architect and plan the verification strategy and execution for sub-system features impacting your unit
Support post-silicon validation activities
What we need to see:
Currently pursuing or recently completed a BS or MS in electrical engineering or computer engineering (or equivalent experience)
Exposure to Computer Architecture, ASIC design and verification methodology is required
Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and test bench design
Understanding of object oriented programming concepts
Good debugging and problem solving skills
Ways to stand out from the crowd:
Experience with assertion-based verification, Semiformal Verification (SFV), Unified Verification Methodology (UVM), SystemVerilog checkers and scoreboards.
Perl or Python knowledge
Experience with multiple verification methodologies
You will also be eligible for equity and .
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